CoCo3FPGA

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The CoCo3FPGA is a hardware synthesis of the Radio Shack Color Computer 3 (aka CoCo3). It is synthesized in HDL and the primary platform is the Terasic DE1 development board. The CoCo3FPGA was created and launched in 2007 by Gary Becker.


CoCo3FPGA on the Terasic DE1
Developer - Gary Becker


Origin and history

Three generations of the Tandy CoCo

The CoCo3FPGA is based upon the original Radio Shack TRS-80 Color Computer which was launched in 1980 and has lasted through three generations of hardware until being discontinued in 1991. After its demise there were several successors from third-party vendors that emerged. Among these were the Tomcat, MM/1, AT306, System IV, and the PT68K-4. Unfortunately, none of these even came close to gaining the popularity of the CoCo 3 primarily because they lacked backward compatibility.

On the other hand, the CoCo3FPGA designed by Gary Becker is broadly compatible with the original CoCo 3 while significantly improving performance and adding enhancements. These include a 25 MHz CPU core, 16-bit audio, VGA video, and higher resolution graphics. The result is a computer that satisfies the retro-computing hobbyist because of its compatibility with the legacy design but also provides an upgrade path for users who wish to exploit some of its new features. For many years, loyal CoCo fans wished for a CoCo 4 successor. There was disagreement among them as to which computer really deserved the name 'Color Computer' or 'CoCo'. Because of the stigma associated with the 'CoCo 4' moniker, the name has remained, 'CoCo3FPGA' much to the chagrin of some users who believe that it has truly become the logical successor to the CoCo 3.

In 2007, Gary Becker began designing what would become the CoCo3FPGA on a Digilent XC3S1000 board. In September of 2008 he created the CoCo3FPGA Yahoo! group and posted the files and documentation to support it. As time went by there was pressure to port the HDL code to a more readily available platform, the Terasic DE1. By May of 2010 Gary had posted versions of his design for both boards. Aside from the design of the main CPU core (6809) and the co-processor (6502) Gary has designed the other components in Verilog HDL. From time to time he freely releases his source files so that others may port the design to other platforms if they wish.

As of October 2017 the CoCo3FPGA group is comprised of over 400 members averaging over 100 posts per month since May of 2015. The group exchanges ideas on programming, development, NitrOS9, and new features. Any interested party may join by navigating to the Yahoo! CoCo3FPGA group and selecting 'Join'. A request to join will normally be approved by a moderator in less than 24 hours.

Performance

MC6809 core

The core CPU of the CoCo3FPGA was designed in VHDL by Australian developer John Kent. The design mimics the operation of the original Motorola 6809 processor which was an engineering marvel of its time. Many of the CPU instructions execute in fewer clock cycles than the original resulting in a processor that is generally around 15% faster than the original Motorola design running at a comparable clock speed.

This results in a more efficient core but also causes some compatibility problems with software that was written for the original Motorola processor and relied upon very precise cycle timing which was calculated from the chip's data sheets.

CPU clock speed

The original Color Computer 3 contained an MC68B09E processor which was rated at a maximum clock speed of 2 MHz. It had the ability to clock the CPU at the normal speed of .89 MHz for compatibility with the older CoCo models and a double speed of 1.78 MHz. BASIC CoCo programmers refer to the method of overclocking as the 'double speed poke'. Using the BASIC 'POKE' command, a couple of registers could be manipulated to change the clock speed of the CPU. POKE 65496,0 selected the normal speed clock and POKE 65497,0 selected the double speed clock. In assembly language this could be accomplished with a CLR $FFD8 (slow) or CLR $FFD9 (fast).

The same procedure still works on the CoCo3FPGA as long as SW0 is in the 'ON' position. When SW0 is in the 'OFF' position, the high speed selection (POKE 65497,0 or CLR $FFD9) actually causes the CPU to clock at 25 MHz which is a huge performance increase compared to the normal .89 MHz speed.

At a 25 MHz clock speed the Kent 6809 core will benchmark at approximately 12 MIPS. In comparison, a MC68000 would have to run at a clock frequency of over 68 MHz to achieve the same benchmark, and an Intel 486DX would have to be clocked at over 30 MHz.

The CoCo3FPGA uses fast SRAM with a 10 nanosecond access time which allows the CPU to run at full speed with no wait states.

SD Card

The DE1 is socketed to accept a full-size SD card. Currently the SD card interface is fully supported under NitrOS9. The interface is accessible from Super Disk Extended Color BASIC but is currently only supported by third-party software.

Disk access speed using the SD card is dramatically improved when compared to floppy disks or even Drivewire access. A disk performance benchmark, 'megaread', under NitrOS9 reports that a one megabyte block of data can be read in about 3-4 seconds using a good quality SD card.

Super Disk Extended Color Basic

The operating system of the CoCo3 when combined with the code for the floppy disk controller is commonly referred to as 'Super Disk Extended Color Basic' (SDECB). The code is contained within a 32K-byte ROM on the main board of the CoCo 3 and an 8K-byte ROM on the FDC board. The CoCo3FPGA uses these two ROMs combined and unmodified.

Since the hardware for the cassette interface has not been synthesized the commands AUDIO ON/OFF, CLOAD, CLOADM, CSAVE, CSAVEM, MOTOR ON/OFF, and SKIPF are non-functional.

Coco3FPGA OS9/NitrOS9

As of Febuary 2017, the Coco3FPGA now has it's own port of NitrOS9 started on the NitrOS9 repository. Though the disk images produced there are bootable as well as usable, they are still a work in progress. Other than a couple of new features, The Coco3FPGA NitrOS9 port currently only supports the standard NitrOS9 Level 2 features, such as screen resolution, joystick support, memory, etc. It is our hope to add support for the extended graphics mode, extended memory, WiFi, and better support for the SD card, which is already supported in a very basic form (SPI mode). Also, support (and drivers) has been added for the RTC (real time clock) found on the "Analog Board" add-on daughter board, and Gary's new 8 megabyte "RamD" ram drive (Analog Board not required).

Coco3 FPGA NitrOS9 Features


The Coco3FPGA NitrOS9 port supports the following features:

  • Standard DE1 Coco3FPGA w/512k:
    • Complete NitrOS9 L2 3.3.0 Support
    • Standard NitrOS9 screen modes
      • 32 x 16 Hardware Text
      • 40 x 24 Hardware Text
      • 80 x 24 Hardware Text
      • 640 x 192 Two Color Graphics w/80 x 24 Text
      • 320 x 192 Four Color Graphics w/40 x 24 Text
      • 640 x 192 Four Color Graphics w/80 x 24 Text
      • 320 x 192 Sixteen Color Graphics w/40 x 24 Text
    • 512k Memory available for processes and graphics (without Analog Board)
    • RS232 port for DriveWire or serial communications (switch selectable)
    • DriveWire support through the Becker Port
    • Rudimentary SD Card Support (SPI mode)
    • 8 Megabyte Ramdisk (does not use system memory)
  • W/Onboard Memory Replacing the 512k with 1 Megabyte:
    • 1 Megabyte of memory available for processes and graphics
  • W/Analog Board:
    • Memory up to 2 Megabytes available for processes and graphics
    • Battery Backed Real Time Clock (RTC)
    • Support for 2nd RS232 port

Coco3FPGA NitrOS9 Ditribution Disk Images:


Currently, the NitrOS9 repository produced 6 disk images specifically for the Coco3FPGA. Each disk image is created for a specific pupose. In this section, I will try to explain the contents of each disk and it's usage.

Bootable NitrOS9 Disk Images

"nos96809l2v030300_coco3fpga_becker.dsk"
This disk is specifically for booting NitrOS9 from the Drivewire server on the Coco3FPGA. The bootfile is configured with "/X0" as "/DD" and includes the "/x1"-"/X3" descriptors.
The SD card is supported with the "/Sd0"-"/SD1" descriptors (128 megabyte each).
The clock uses the Drivewire clock module and must always be connected to Drivewire.
Gary's 8 megabyte ramdisk dirver is also included.
A good use for this boot image is for setting up and formatting the SD card partitions for the first time.
This Os9Boot requires Drivewire to run.
It does not require the Analog Board.
"nos96809l2v030300_coco3fpga_becker_sd.dsk"
This disk is specifically for booting NitrOS9 from the Drivewire server on the Coco3FPGA, but must have "/SD0" populated with the system files and CMDS.
The bootfile is configured with "/SD0" as "/DD", making "/SD0" the system drive.
The Drivewire drivers are the "/X0"-"/X3" descriptors. The remaining SD card partition is the "/Sd1" descriptor (128 megabyte each).
The clock uses the Drivewire clock module and must always be connected to Drivewire.
Gary's 8 megabyte ramdisk dirver is also included.
This OS9Boot is for booting to the SD card using Drivewire, for those not using Brett Gordon's BootRom.
This Os9Boot requires Drivewire to run. It does not require the Analog Board.
"nos96809l2v030300_coco3fpga_becker_sd_rtc.dsk"
This disk requires drivewire for booting only.
It does require "/SD0" ("/DD"), to be populated with system files and CMDS.
Once booted, Drivewire is not needed, but is accessable though the "/X0"-"/x3" descriptors.
The SD card descriptors are "/DD", & "/SD1" (128 megabyte each).
The clock uses the RTC driver for the real time clock on the Analog Board and therefore requires the Analog Board to run.
Drivewire is only required for booting.

Images for Copying to the SD Card System Partition

These images are NOT bootable disks but are meant to be copied to the main SD card partition to be booted by Brett Gordon's Coco3FPGA bootrom.

"nos96809l2v030300_coco3fpga_bootrom.img"
This is NOT a bootable image. This image is meant to copied to the main NitrOS9 SD card partition and booted using Brett Gordon's bootrom for the Coco3FPGA.
Drivewire is NOT required to but but is available if needed. This is an "untethered" Coco3FPGA boot image.
The SD card driver/descriptors "/DD" ("/SD0") & "/SD1" are present for use of the SD card.
The Drivewires drivers/descriptors are included but are not required to boot.
Gary's 8 megabyte ramdisk is included.
The image includes the "softclock" software OS9 clock and does NOT need Drivewire to boot.
Does NOT require the Analog Board.
"nos96809l2v030300_coco3fpga_bootrom_becker.img"
This is NOT a bootable image. This image is meant to copied to the main NitrOS9 SD card partition and booted using Brett Gordon's bootrom for the Coco3FPGA.
Drivewire IS required to boot this image.
The SD card driver/descriptors "/DD" ("/SD0") & "/SD1" are present for use of the SD card.
The Drivewires drivers/descriptors ("/X0"-"/X3") are included but are not required to boot.
Gary's 8 megabyte ramdisk is included.
The image includes the Drivewire OS9 clock and DOES need Drivewire to boot.
Does NOT require the Analog Board.
"nos96809l2v030300_coco3fpga_bootrom_rtc.img"
This is NOT a bootable image. This image is meant to copied to the main NitrOS9 SD card partition and booted using Brett Gordon's bootrom for the Coco3FPGA.
Drivewire is NOT required to but but is available if needed. This is an "untethered" Coco3FPGA boot image.
The SD card driver/descriptors "/DD" ("/SD0") & "/SD1" are present for use of the SD card.
The Drivewires drivers/descriptors are included but are not required to boot.
Gary's 8 megabyte ramdisk is included.
The image includes the Coco3FPGA Analog Board RTC OS9 clock driver and does NOT need Drivewire to boot.
This image DOES require the Analog Board.

Onboard hardware

Serial port

VGA display

The Radio Shack Color Computer 3 has a number of different text and graphics modes but all were designed to be displayed on either a TV, composite NTSC color monitor, or an RGB monitor with 15.75 kHz horizontal line rate. Since these types of displays are now outdated and almost obsolete, the CoCo3FPGA displays all video output using a 640x480 60Hz VGA signal. The connector is a standard female DE15HD connector commonly used for VGA displays on PCs and other computers. The data for the pixels are clocked at 25 MHz with four bits of resolution per color.

The CoCo3FPGA adds a new video mode that displays up to 256 different colors from a palette of 4096 colors on a 640x450 resolution screen. Some YouTube links to demonstrations of this new mode can be found at: CoCo3FPGA 256 color line drawing demo ,ShowBMP program displaying 256-color BMP images , Line drawing demo with VGA font .

SRAM 'New' vs 'Old'

Users of the Terasic DE1 have found that at least two different types of SRAM chips have been used in production of these boards. The most recently produced boards use an IS61WV25616BLL-10 chip while older boards used a IS61LV25616AL-10 chip. The two versions of SRAM have slightly different timing characteristics and the later versions (WV prefix) seemed to be more problematic during the early development stages of the CoCo3FPGA. Developers for other retro computing projects (notably the Sinclair ZX Spectrum and the Atari Amiga) also faced the same problems. Gary Becker, the developer of CoCo3FPGA, was able to work out the timings for both SRAMs so that the core CPU could run at a clock speed of 25 MHz. However, depending on which chip is used in any particular DE1, the user will have to select an HDL programming file that corresponds with either the 'Old' (IS61LV25616AL-10) or 'New' (IS61WV25616BLL-10) SRAM.

Flash Memory

The flash memory on the DE1 is a 4MB parallel NAND chip made by Spansion (Cypress Semiconductor). Several different part numbers have been used on the DE1 boards but they are generally variants of the S29 series and usually have a 70 or 90 nanosecond access time. The flash memory holds, among other things, the contents of the original Tandy Color Computer 3 ROM and the disk controller ROM. Two methods are currently available for programming the flash memory. Terasic supplies a program called 'Control Panel' which uses the USB Blaster interface to send data to the DE1. For certain users the Control Panel software has proven to be quite problematic and finicky. The second method involves using a program written by Dave Philipsen called 'Flash-uploader' which communicates with the DE1 via the serial interface using a terminal program with xmodem protocol.

The CoCo ROMs are the only required contents that need to be copied to the flash memory in order for the CoCo3FPGA to work. Additional data may be copied to the flash such as the Orch-90 ROM, various Program Pak ROMS, a secondary disk controller ROM, and NitrOS9 boot ROMs. See the information on MPI slots and slot switching using SW1 and SW2 for details. In addition, the Multi Cartridge ROM System (MCRS) is discussed in detail in another part of this document.

Because the flash memory has a slower access speed it cannot be read by the processor when it is running at 25 MHz. The CPU core must be slowed down in order to read the flash. This is not normally a problem since the CoCo 3 mostly runs in all RAM mode and the contents are copied from flash memory to RAM at boot time.

In addition to programming the flash using the Control Panel or Flash-uploader programs, an interface is available for user programs to access and program it. By default the Flash is write protected. But a special feature has been added to enable the Flash to be programmed. This uses the Multiple Cartridge ROM System and the ability to unlock the write protect on the Flash. To unlock the write protect and map a section of the Flash into slot 3 address space:

1 Turn off Interrupts (Turns off all RAM mode)

2 Write to $FFDE data does not matter (Enable 32K external ROM)

3 Set bits 0 and 1 of $FF90 (These next two steps change to slot 3 and removes the write protect for the Flash)

4 Write $2A into $FF7F

5 Write $26 into $FF7F (Enable MCRS bank 0)

6 Write 0 into $FF40 (Bank 0 address, the 7 address bits should be located in the low 7 bits of the data)

7 Write the Flash Address 15 to 21 bits of the Flash Address into $FF42

8 Write Flash Address bit 14 * 2 + 1 into into $FF43

SDRAM

The DRAM chip on the DE1 board is an 8-megabyte part. Though the DRAM is not used for standard system memory on the 6809 core there is an interface present in the CoCo3FPGA for its use. Gary has written a driver for NitrOS9 which allows it to be used as a ramdisk. The ramdisk appears to be faster than the SD card access with a 'megaread' time of about 1.25 seconds (SD card is around 3.75 seconds).

SD Card

PS/2 keyboard port

The DE1 board sports a 6-pin mini DIN jack which is used for a PS/2-style keyboard which and by means of synthesis in the FPGA the keyboard then emulates the matrix of the original CoCo 3 keyboard. Some notable additions to the functionailty of the keyboard:

Pressing CTL-ALT-DEL issues a hardware reset
Pressing CTL-ALT-INS causes a cold start
Some extra keys found on the PS/2 keyboard but not on the CoCo are mapped as follows:

$FFCC
Bit 7 = Alt
Bit 6 = Control
Bit 5 = Right Shift
Bit 4 = Left Shift
Bit 3 = Down Arrow
Bit 2 = Up Arrow
Bit 1 = Right Arrow
Bit 0 = Left Arrow

$FFCD
Bit 7 = Page Down
Bit 6 = Page Up
Bit 5 = Insert
Bit 4 = Delete
Bit 3 = Home
Bit 2 = End
Bit 1 = 
Bit 0 = 

$FFCE
Bit 7 = F8
Bit 6 = F7
Bit 5 = F6
Bit 4 = F5
Bit 3 = F4
Bit 2 = F3
Bit 1 = F2
Bit 0 = F1

$FFCF
Bit 7 = V-Sync
Bit 6 = V-Border
Bit 5 = H-Sync
Bit 4 = H-Border
Bit 3 = F12
Bit 2 = F11
Bit 1 = F10
Bit 0 = F9

Audio

LEDs

Configuration

Slide switches

The DE1 has 10 slide switches across the front labeled SW0-SW9. These switches allow for certain configuration options to be set. The 'off' position is down or toward the edge of the board.


SW0                  CPU Speed      
------------------------------
OFF                   1.78 MHz
ON                      25 MHz


SW2 / SW1      MPI Slot select
------------------------------
OFF / OFF                    1
OFF /  ON                    2
ON  / OFF                    3
ON  /  ON                    4


SW3  Intensity on every 
     other scan line 
------------------------------
OFF             Full intensity
ON              Half intensity


SW4  Disable autostart interrupt
     for slots 1 & 3
--------------------------------
OFF           Interrupt disabled
ON             Interrupt enabled


SW5       Semi-graphics mode 6
------------------------------
OFF                   Disabled
ON                     Enabled


SW6  SD card WP & removal
     detection
------------------------------
OFF                    Enabled
ON                    Disabled


SW8 / SW7    Serial port speed
------------------------------
OFF / OFF          115,200 bps
OFF /  ON          230,400 bps
ON  / OFF          460,800 bps
ON  /  ON          921,600 bps


SW9                               UART swap
-------------------------------------------
OFF   Drivewire on DE1 / RS232 on expansion
ON    RS232 on DE1 / Drivewire on expansion

Expansion board

Expansion board on the Terasic DE1

In June of 2015 Gary Becker queried the CoCo3FPGA user group to see if there was interest in the design and production of an expansion board. He proposed that the board would include a pair of CoCo3 compatible Joystick ports, an extra RS232 PAK serial port, and maybe an RTC. The DE1 has neither an ADC nor an RTC. Through the winter of 2015/16 he designed the board and actually surprised everyone by adding two fast 2MB SRAM chips and a WiFi module as well as a prototyping area. The first boards were actually designed by Gary and several members of the group built them as a kit. By the end of March 2016 he had written code to support the board with a whopping 4MB of extra memory and was booting NitrOS9 and demonstrating that the 'mfree' command showed 2MB of memory which is the maximum it recognizes. Apparently only three of these boards were ever produced and it is referred to as the 'Gary' board.

Gary turned over small scale production of the board to Ed Snider (Zippster) for fulfillment of orders. Ed did a fairly drastic re-design on the board changing the layout and streamlining to have as few vias as possible. The result was a new expansion board that still had the same features but was more of a production ready design. Some mechanical improvements were made and Ed bundled the board with standoffs and other extras so that the final product looked pretty professional.

Keyboard

Since the CoCo3FPGA uses a PS/2 keyboard there are some minor differences that must be taken into consideration:

From DECB, use 'Caps Lock' to toggle between lower case/upper case instead of SHIFT-0

Some information on extra keys (to be explained in more detail in the future):

$FFCC
Bit 7 = Alt
Bit 6 = Control
Bit 5 = Right Shift
Bit 4 = Left Shift
Bit 3 = Down Arrow
Bit 2 = Up Arrow
Bit 1 = Right Arrow
Bit 0 = Left Arrow

$FFCD
Bit 7 = Page Down
Bit 6 = Page Up
Bit 5 = Insert
Bit 4 = Delete
Bit 3 = Home
Bit 2 = End
Bit 1 = 
Bit 0 = 

$FFCE
Bit 7 = F8
Bit 6 = F7
Bit 5 = F6
Bit 4 = F5
Bit 3 = F4
Bit 2 = F3
Bit 1 = F2
Bit 0 = F1

$FFCF
Bit 7 = V-Sync
Bit 6 = V-Border
Bit 5 = H-Sync
Bit 4 = H-Border
Bit 3 = F12
Bit 2 = F11
Bit 1 = F10
Bit 0 = F9

Drivewire 4 support

Drivewire server software

In the 1980s when the Tandy Color Computer was first released, the 5-1/4" floppy disk was the affordable choice for data and program storage on most personal computers. The 5-1/4" floppy format was succeeded by the 3-1/2" disk (commonly referred to as a 'floppy' but, in reality, not floppy!). Today, the floppy disk is practically non-existent and it has been obsoleted with the advent of USB drives, CDs, DVDs, SD cards, inexpensive hard drives, etc. Boisy Pitre and Aaron Wolfe developed a novel solution to address the problem of storage for users wishing to experience retro computing with the Color Computer without having to rely upon floppy disks or hard drives. The Drivewire server uses a modern host computer to provide storage via serial data link to the client. In addition to data storage a number of other features such as drives as large as 4GB, access to remote filesystems, TCP/IP networking, virtual/telnet modem emulation, emulated Epson FX80 printing, real time clock, MIDI, etc. are supported.

The CoCo3FPGA supports Drivewire natively without the need for an external program or modified system ROMs. This is accomplished using a 6502 co-processor that runs in the background trapping hardware accesses to the floppy disk controller and converting them to the serial protocol used by Drivewire. The biggest limitation is the bottleneck created by the RS232 serial ports on the host and client which generally do not support rates higher than 230.4 kbps. This limitation means that in most cases the Drivewire server works faster than a typical floppy drive but slower than most hard drives.

Port to DE2

Terasic DE2

On October 30, 2015 Leslie Ayling announced the porting of the CoCo3FPGA to the Terasic DE2. The DE2 is essentially an expanded version of the DE1 with an FPGA containing more logic elements and some added on-board features.








Becker port

The "Becker" port is a simple interface used in the CoCo3FPGA project (and some CoCo emulators) to allow high speed I/O between the CoCo3FPGA and the DriveWire server.

The interface uses 2 addresses, one for status and one for the actual I/O.

The read status port is &HFF41

The only bit used out of bit 0 to bit 7 is bit #1

If there is data to read then bit #1 will be set to 1

The read/write port is &HFF42

When reading you must make sure you only read when data is present by the status bit.

As far as writing you just write the data to the port.

Downloads

Current design files

SOF (temporary programming)

POF (permanent programming)

Demo programs

While a very large number of programs originally written for the Color Computer 3 will run on the CoCo3FPGA, several programs have been written to take advantage of some of its new features. In April of 2016 Dave Philipsen released a program which used the 256-color 640 x 450 graphics mode displaying EGA/VGA character fonts with line drawing characters for a demonstration at the 25th annual Last CoCoFest in Chicago. The program also made use of an accelerated memory access feature which bypasses the MMU to allow faster access to a memory range greater than 64k. In May of 2016 Richard Goedeken updated his RAM stress test program to handle up to 8 megabytes of memory which was needed in order to test the RAM on the newly-available RAM/analog expansion board.

OS9 Drivers

Summary

See also

References

External links